The present invention relates to a semiconductor device and a method of manufacturing the same.
A metal gate transistor can be manufactured, for example, through a damascene gate electrode formation process as disclosed in Japanese Patent Laid-open (Unexamined) Publication No. H04-123439 (1992).
FIGS. 23A to 23C are sectional views illustrating part of process steps of a prior art manufacturing process of a damascene gate transistor.
First, as can be seen in FIG. 23A, a silicon substrate 31, which is provided with shallow trench isolations (STIs) 32 serving as device isolation film in advance, is superposed with an oxidation film 33, and then is formed with dummy gate electrodes 34a and 34b, respectively, over the oxidation film. The dummy gate electrode 34b in the figure is designed to be larger in lateral width than the dummy gate electrode 34a. With masks of the dummy gate electrodes 34a and 34b, impurities are implanted in the silicon substrate 31 to form source and drain regions 35a and 35b. After that, an interlayer insulation film 36, which may be an oxidation film, is deposited to cover the dummy gate electrodes 34a and 34b, for example.
Then, as shown in FIG. 23B, the interlayer insulation film 36 undergoes chemical mechanical polishing (CMP) to flatten the surface, and thus, the dummy gate electrodes 34a and 34b have their respective top sides exposed.
Next, as illustrated in FIG. 23C, the dummy gate electrodes 34a and 34b are removed by chemical dry etching (CDE) to form gate trenches 37a and 37b. After that, the gate trenches 37a and 37b are filled with metal to form gate electrodes (not shown), respectively.
References related to the present invention are as follows:                (1) Japanese Patent Laid-open Publication No. H12-294557, and        (2) Japanese Patent Laid-open Publication No. H04-123439.        
In such a damascene gate electrode formation process, however, as can be seen in FIG. 23A, the interlayer insulation film 36 is deposited over the dummy gate electrode 34b occupying a wider range, compared to that over the dummy gate electrode 34a. Hence, a polishing rate to the insulation film by means of CMP is slower over the dummy gate electrode 34b than over the dummy gate electrode 34a, and when the CMP is completed, a residual insulation film 36′ overlies the dummy gate electrode 34b, as recognized in FIG. 23B. Hence, as is apparent in FIG. 23C, while the dummy gate electrode 34b is being etched away, the residual interlayer insulation film 36′ inhibits the underlying electrode from being etched. To cope with this, the CMP may be carried out for an extended period of time and ensure that the layer insulation film 36′ can be removed from the top of the dummy gate electrode 34b in advance. With this option of the extended CMP, however, the interlayer insulation film 36 is overpolished in a region free from the dummy gate, which results in an undesirably reduced thickness of the interlayer insulation film.
In order to avoid a trouble of the residual film over the dummy gate electrode 34b, as described in more details in conjunction with FIGS. 24A and 24B, one alternative is selectively etching part of the interlayer insulation film 36 from the top of the dummy gate electrode 34b. According to this method, as can be seen in FIG. 24B, the polishing rate is almost identical in either region over the dummy gate electrode 34a or over the dummy gate electrode 34b, and the finish is uniform throughout the polished surface. Thus, the aforementioned problem of overpolishing no longer occurs. In this manner, however, another trouble of dishing is caused, which will be detailed below.
FIGS. 24A to 24C and FIGS. 25A and 25B are cross-sectional views illustrating steps of the damascene gate electrode formation process which follows the above-mentioned way.
An area A1 on the left half of each figure is indicative of a device formation area where devices such as damascene gate electrodes and the like are to be formed. An area A2 on the light half of each figure is indicative of a target area where targets for alignment and/or inspection targets for misalignment are to be formed. Herein, A3 denotes a mark area. The mark area A3 is formed as an area of photoresist film which is used during a alignment of a substrate with a photomask in a photolithography process and which is patterned so as to match with alignment marks in a reticle (photomask) or marks for forming inspection targets for misalignment. In other words, this is an area of photoresist film that has a pattern, such as the alignment marks of the substrate with the photomask, traced during a procedure of exposure to light with the photomask.
The damascene gate electrode formation process will now be described in details.
First, as shown in FIG. 24A, a substrate 31, which is provided in advance with shallow trench isolations (STIs) 32 serving as device isolation film and targets 40(1), 40(2), 40(3), and so forth used for alignment, has its surface formed with an oxidation film 33 by for example thermal oxidation, and after that, polysilicon is deposited thereover and then patterned to leave the dummy gate electrodes 34a and 34b. Next, with masks of the dummy gate electrodes 34a and 34b, impurity ions are implanted and diffused to form the source and drain regions 35a and 35b, respectively. Then, the interlayer insulation film 36 such as silicon oxidation film is deposited to cover the dummy gate electrodes 34a and 34b. Furthermore, a photoresist film is deposited by means of spin coating, and then, the lithography method is used to pattern the surface into a photoresist film 38 which serves to selectively etch the interlayer insulation film 36.
The process of the pattering into the photoresist film 38 will now be detailed.
A photomask (not shown) patterned into a desired design is aligned with the substrate. This is attained by a position matching of alignment marks in the photomask with the target 40(2) formed in the target area A2 throughout the substrate 31. When aligned, the substrate 31 is exposed to light and then developed. In this way, the resist film is patterned and then used to selectively remove the interlayer insulation film 36 from the top of the dummy gate electrode 34b. The exposure and development provide the resist film with a pattern (or a CMP auxiliary mask) 39 that matches with a pattern of the alignment marks. A plan view of the CMP auxiliary mask 39 is illustrated in FIG. 26. A sectional view of the CMP auxiliary mask 39 along the line D—D in FIG. 26 is represented as the CMP auxiliary mask 39 in FIG. 24A.
As can be seen in FIG. 24B, the photoresist film 38 is used to selectively remove the interlayer insulation film 36 from the top of the dummy gate electrode 34b by an appropriate means of anisotropic etching such as reactive ion etching (RIE). At this stage of the process, the interlayer insulation film 36 beneath the mark area A3 is to be selectively etched, and eventually, after the interlayer insulation film 36 is etched away, the silicon substrate (or the oxidation film 33) is exposed.
Then, as recognized in FIG. 24C, the interlayer insulation film 36 is flattened by means of CMP to expose upper surfaces of the dummy gate electrodes 34a and 34b, respectively.
Next, as shown in FIG. 25A, the exposed dummy gate electrodes 34a and 34b are etched away to form gate trenches 42a and 42b. 
After that, as can be seen in FIG. 25B, the silicon substrate 31 has its exposed surface or oxidation film 30 etched away, and then, it has its etched surface superposed with a gate insulation film 50 of oxide. In addition to that, the gate trenches 42a and 42b are filled with a material such as polysilicon, metal or the like, to create gate electrodes 43a and 43b, respectively.
In the above mentioned stage of CMP (FIG. 24C), however, part of the silicon substrate 31 beneath the mark area A3 is polished as well as part of the interlayer insulation film 36 around the mark area A3; that is, the pattern (i.e., film thickness) of the interlayer insulation film 36 around the mark area A3 is altered. This altered patterning is called dishing and designated by a reference numeral 41. When the film thickness of the interlayer insulation film 36 is altered, the targets 40(1) and 40(3), if used as targets for alignment, for example, in forming an additional layer over the interlayer insulation film 36, might be read with increased errors. Such errors, when increased in reading the targets such as the targets 40(1) and 40(3), further lead to adverse effects like misalignment of layers stacked over the substrate.